The present invention relates to a static column dynamic random access memory device and aims at reducing the power consumption in such a memory device.
In recent years, the demand for a dynamic random access memory device (hereinafter referred to as a DRAM) with a higher speed has been increasing. One solution to meet this demand is a static column DRAM, as disclosed in Nikkei Electronics (1983, Vol. 9, No. 12, pp 153-174, published in Japan).
In the static column DRAM, once the row address has been latched within the chip by means of a row address strobe signal (hereinafter referred to as a RAS chip signal), a high speed access (as in a static RAM) to the row whose row address has been latched can be made responsive to a column address, and the static column DRAM does not require a column address strobe signal (hereinafter referred to as a CAS signal) which the conventional DRAM required. The columns circuits of the static column DRAM are therefore automatically activated after the completion of the row circuits' operation which was initiated upon the RAS signal falling to "L" level. To alleviate restrictions on timing in use, it is generally arranged so that, once a series of the operations in a memory cycle are started (upon the RAS signal falling to "L"), the memory operations are not interrupted until the end even if the RAS signal is raised to "H" in the middle of the operations.
An example of a prior art static column DRAM is shown in FIGS. 1A and 1B. As shown, it comprises a memory cell array 1 comprising a plurality of memory cells MC arranged in rows and columns to form a matrix, a row decoder 2 for selecting the word lines WL, a row address buffer 3, a row of sense amplifiers 4 amplifying the information read from the memory cells onto the respective bit lines BL, an input/output gate 5, a column decoder 6, a column address buffer 7, a data output buffer 8, a data input buffer 9, a row timing control circuit 10, a write control circuit 11, an output control circuit 12, an inverter 21 and an OR gate 22.
RAS denotes the RAS signal. WE and CS respectively denote a write signal and a chip select signal. These control signals are supplied from outside. .PHI.RAS denotes an internal RAS (row address strobe) clock. .PHI.RA denotes a clock for latching the row address in the row address buffer 3. .PHI.WL denotes a clock for activating the word line which has been selected by the row decoder 2. .PHI.SA is a clock for activating the sense amplifiers 4. .PHI.REF denotes a clock indicating that a refresh operation is under execution. .PHI.CE denotes a clock for activating the column circuits. .PHI.WR denotes a clock for write control. .PHI.WC denotes a clock indicating that a write operation is under execution. .PHI.OE is a clock for output control.
The operations of the memory shown in FIGS. 1A and 1B will now be described with reference to FIG. 2. At time t1, the RAS signal falls to "L". The clock .PHI.RAS, and then the clocks .PHI.REF and .PHI.RA rise to "H". The row address is latched by the row address buffer 3, and decoding by the row decoder 2 is conducted. Upon completion of the decoding, the clock .PHI.WL rises and the word line designated by the row address is activated. The information stored in the memory cells connected to the selected word line is read out onto the bit lines BL, after which the clock .PHI.SA rises to "H" so that the sense amplifiers 4 start refreshing the information.
At time t2, the refreshing is completed. Then, the clock .PHI.REF falls to "L" and the clock .PHI.CE simultaneously rises to "H". As shown in FIG. 1, the clock .PHI.RAS is a logical sum (OR) of the inversion of the RAS signal and the clocks .PHI.REF and .PHI.WC. As a result, once the clock .PHI.REF rises to "H" (because of the RAS signal of "L"), the refresh operation is completed even if the RAS signal rises to "H" before the time t2, as illustrated by the solid lines in FIG. 2. If the RAS signal is held "L" until the time t3, i.e., after t2, as illustrated by the broken lines in FIG. 2, the CS signal and WE signal are kept supplied, so that read/write memory operations can be conductived (not illustrated).
In the prior art memory, the clock .PHI.CE for activating the column circuits is triggered upon the clock .PHI.REF falling indicating completion of the refresh operation. As a result, in a RAS only refresh cycle in which only the refreshing is required and the column circuits need not operate, there is a period in which the clock .PHI.CE is at "H". During this period, unnecessary power consumption occurs in the column circuits.